1. Field of the Invention
The present invention relates to flash memory technology, and more particularly to scalable charge trapping memory technology adaptable for high speed erase and program operations.
2. Description of Related Art
Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory employs floating gate memory cells. As the density increases in memory devices, and the floating gate memory cells get closer and closer together, interference between the charge stored in adjacent floating gates becomes a problem. This interference limits the ability to increase the density of flash memory based on floating gate memory cells. Another type of memory cell used for flash memory can be referred to as a charge trapping flash memory cell, which uses a dielectric charge trapping layer in place of the floating gate. Charge trapping memory cells use dielectric charge trapping material that causes much less cell-to-cell interference than that encountered with floating gate technology, and is expected to be applied for higher density flash memory.
The typical charge trapping memory cell consists of a field effect transistor FET structure having a source and drain separated by a channel, and a gate separated from the channel by a stack of dielectric material including a tunnel dielectric layer, the charge storage layer, and a blocking dielectric layer. According to the early designs referred to as SONOS devices, the source, drain and channel are formed in a silicon substrate (S), the tunnel dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed a silicon oxide (O), and the gate comprises polysilicon (S). The SONOS device is programmed by electron tunneling using one of a number of well-known biasing technologies, and erased by hole tunneling or electron de-trapping. In order to achieve practical operational speeds for the erase operation, the tunneling dielectric layer must be quite thin (less than 3 nm). However at that thickness, the endurance and charge retention characteristics of the memory cell are poor relative to traditional floating gate technology. On the other hand, the electric field required for the erase operation using thicker tunneling dielectric layers also causes electron injection from the gate through the blocking dielectric layer. This electron injection causes an erase saturation condition in which the charge level in the charge trapping device converges on an equilibrium level. See, U.S. Pat. No. 7,075,828, entitled “Operation Scheme with Charge Balancing Erase for Charge Trapping Non-Volatile Memory”, invented by Lue et al. However, if the erase saturation level is too high, the cell cannot be erased at all, or the threshold margin between the programmed and erased states becomes too small for many applications.
Technology has been investigated to improve the ability of the blocking dielectric layer to reduce electron injection from the gate for the high electric fields needed for erase. See, U.S. Pat. No. 6,912,163, entitled “Memory Device Having High Work Function Gate and Method of Erasing Same,” Invented by Zheng et al., issued 28 Jun. 2005; and U.S. Pat. No. 7,164,603, entitled “Operation Scheme with High Work Function Gate and Charge Balancing for Charge Trapping Non-Volatile Memory”, invented by Shih et al., Shin et al., “A Highly Reliable SONOS-type NAND Flash Memory Cell with Al2O3 or Top Oxide,” IEDM, 2003 (MANOS); and Shin et al., “A Novel NAND-type MONOS Memory using 63 nm Process Technology for a Multi-Gigabit Flash EEPROMs”, IEEE 2005.
Also, technology has been investigated to improve the performance of the tunneling dielectric layer for erase at lower electric fields. See, U.S. Patent Application Publication No. US 2006/0198189 A1, “Non-Volatile Memory Cells, Memory Arrays Including the Same and Method of Operating Cells and Arrays,” Invented by Lue et al., publication date Sep. 7, 2006 (describing a “BE-SONOS device”); Lue et al., “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability”, IEEE, December 2005; Wang et al., “Reliability and Processing Effects of the Bandgap Engineered SONOS (BE-SONOS) Flash Memory,” IEEE, May 2007. See also, U.S. Patent Application Publication No. 2006/0261401 A1, entitled “Novel Low Power Non-Volatile Memory and Gate Stack”, by Bhattacharyya, published 23 Nov. 2006. BE-SONOS devices have a three layer dielectric tunneling structure that, as explained in more detail below, includes a first layer of silicon dioxide, typically less than 1.5 nm thick (called herein the “tunneling layer”), a layer of silicon nitride, typically less than 2.5 nm thick (called herein the “band offset layer”), and a third layer of silicon dioxide, typically less than 3 nm thick (called herein the “isolation layer”). Significant performance improvements have been provided by this 3 layer structure, relative to the single layer tunneling dielectric, and other attempts at engineering the tunneling dielectric, by taking advantage of the complex tunneling behavior during relatively low electric field operating modes in which charge retention is necessary, during relatively high positive electric field operating modes in which charge tunneling to increase the device threshold is required, and during relatively high negative electric field operating modes in which charge tunneling to decrease device threshold is required.
BE-SONOS technology has been proven to provide excellent performance, overcoming many of the erase speed, endurance and charge retention issues of prior art SONOS type memory. While the BE-SONOS structure provides excellent reliability, the erase speed remains limited. So, it is desirable to further improve erase speeds for charge trapping memory cells, without sacrificing endurance and retention, so that speeds approach those possible using floating gate technologies.